As the semiconductor field continues to drive enhancements to circuit density scaling, new channel architectures are becoming more relevant. One of the existing ways to extend silicon is horizontal gate all around (hGAA) nanowires. Early hGAA device readouts indicate improved short channel drain induced barrier lowering (DIBL) and subthreshold slope (SS) performance versus finFET lots. Further, decent saturation threshold voltage (Vtsat)—ion performance is achieved with hGAA devices which is on the same trend line as finFET. Moreover, there is no apparent resistance degradation compared with finFET. However, despite the benefits, existing hGAA technology has been focused on unipolar devices.
Currently, there are no nanowire integration schemes that support different nanowire stacks to support multiple devices, and there is no existing complementary metal-oxide-semiconductor (CMOS) integration of multiple nanowires.
A need therefore exists for methodology enabling CMOS integration of multiple nanowires to maximize device offering capability and the resulting devices.